Subversion Repositories i2c

[/] - Rev 64


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 4874d 20h /
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 4874d 21h /
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 4875d 11h /
61 Removed synopsys link; it's not used rherveille 5529d 22h /
60 Added missing semicolons ';' on endif rherveille 5706d 19h /
59 fixed short scl high pulse after clock stretch rherveille 5711d 20h /
58 fixed (n)ack generation rherveille 5743d 22h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 5743d 22h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 6296d 20h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 6297d 22h /
54 Fixed scl, sda delay. rherveille 6297d 22h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 6593d 19h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 6593d 20h /
51 Fixed simulation issue when writing to CR register rherveille 6647d 21h /
50 *** empty log message *** rherveille 6662d 15h /
49 Added testbench rherveille 6662d 16h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 6663d 23h /
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 6672d 19h /
46 Fixed slave address MSB='1' bug rherveille 6747d 20h /
45 Added slave address configurability rherveille 6747d 20h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2022, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.