OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] - Rev 66

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
66 Fixed type iscl_oen instead of scl_oen rherveille 5567d 20h /
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5568d 06h /
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation		 rherveille 5568d 06h /
63 Added clock synchronization logic
Fixed slave_wait signal		 rherveille 5568d 06h /
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits		 rherveille 5568d 20h /
61 Removed synopsys link; it's not used rherveille 6223d 07h /
60 Added missing semicolons ';' on endif rherveille 6400d 04h /
59 fixed short scl high pulse after clock stretch rherveille 6405d 06h /
58 fixed (n)ack generation rherveille 6437d 07h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal		 rherveille 6437d 07h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.		 rherveille 6990d 05h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.		 rherveille 6991d 07h /
54 Fixed scl, sda delay. rherveille 6991d 07h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7287d 04h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7287d 05h /
51 Fixed simulation issue when writing to CR register rherveille 7341d 06h /
50 *** empty log message *** rherveille 7356d 01h /
49 Added testbench rherveille 7356d 01h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7357d 08h /
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7366d 05h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.