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Rev Log message Author Age Path
66 Fixed type iscl_oen instead of scl_oen rherveille 5253d 12h /
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5253d 22h /
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 5253d 22h /
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 5253d 22h /
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 5254d 12h /
61 Removed synopsys link; it's not used rherveille 5908d 23h /
60 Added missing semicolons ';' on endif rherveille 6085d 20h /
59 fixed short scl high pulse after clock stretch rherveille 6090d 22h /
58 fixed (n)ack generation rherveille 6122d 23h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 6122d 23h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 6675d 21h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 6676d 23h /
54 Fixed scl, sda delay. rherveille 6676d 23h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 6972d 20h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 6972d 21h /
51 Fixed simulation issue when writing to CR register rherveille 7026d 22h /
50 *** empty log message *** rherveille 7041d 17h /
49 Added testbench rherveille 7041d 17h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7043d 00h /
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7051d 21h /

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