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Rev Log message Author Age Path
67 Fixed slave_wait clocked event syntax rherveille 5639d 06h /
66 Fixed type iscl_oen instead of scl_oen rherveille 5654d 06h /
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5654d 16h /
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 5654d 16h /
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 5654d 16h /
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 5655d 06h /
61 Removed synopsys link; it's not used rherveille 6309d 18h /
60 Added missing semicolons ';' on endif rherveille 6486d 15h /
59 fixed short scl high pulse after clock stretch rherveille 6491d 16h /
58 fixed (n)ack generation rherveille 6523d 18h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 6523d 18h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 7076d 15h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 7077d 17h /
54 Fixed scl, sda delay. rherveille 7077d 17h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7373d 15h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7373d 16h /
51 Fixed simulation issue when writing to CR register rherveille 7427d 16h /
50 *** empty log message *** rherveille 7442d 11h /
49 Added testbench rherveille 7442d 11h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7443d 19h /

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