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Rev Log message Author Age Path
68 New directory structure. root 4824d 10h /
67 Fixed slave_wait clocked event syntax rherveille 4857d 12h /
66 Fixed type iscl_oen instead of scl_oen rherveille 4872d 12h /
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 4872d 22h /
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 4872d 22h /
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 4872d 22h /
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 4873d 12h /
61 Removed synopsys link; it's not used rherveille 5527d 23h /
60 Added missing semicolons ';' on endif rherveille 5704d 20h /
59 fixed short scl high pulse after clock stretch rherveille 5709d 22h /
58 fixed (n)ack generation rherveille 5741d 23h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 5741d 23h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 6294d 21h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 6295d 23h /
54 Fixed scl, sda delay. rherveille 6295d 23h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 6591d 21h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 6591d 21h /
51 Fixed simulation issue when writing to CR register rherveille 6645d 22h /
50 *** empty log message *** rherveille 6660d 17h /
49 Added testbench rherveille 6660d 17h /

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