Subversion Repositories i2c

[/] - Rev 68


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
68 New directory structure. root 5471d 06h /
67 Fixed slave_wait clocked event syntax rherveille 5504d 09h /
66 Fixed type iscl_oen instead of scl_oen rherveille 5519d 08h /
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5519d 18h /
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 5519d 18h /
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 5519d 19h /
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 5520d 08h /
61 Removed synopsys link; it's not used rherveille 6174d 20h /
60 Added missing semicolons ';' on endif rherveille 6351d 17h /
59 fixed short scl high pulse after clock stretch rherveille 6356d 18h /
58 fixed (n)ack generation rherveille 6388d 20h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 6388d 20h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 6941d 17h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 6942d 20h /
54 Fixed scl, sda delay. rherveille 6942d 20h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7238d 17h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7238d 18h /
51 Fixed simulation issue when writing to CR register rherveille 7292d 19h /
50 *** empty log message *** rherveille 7307d 13h /
49 Added testbench rherveille 7307d 13h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.