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Rev Log message Author Age Path
68 New directory structure. root 5513d 11h /
67 Fixed slave_wait clocked event syntax rherveille 5546d 13h /
66 Fixed type iscl_oen instead of scl_oen rherveille 5561d 13h /
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5561d 23h /
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 5561d 23h /
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 5561d 23h /
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 5562d 13h /
61 Removed synopsys link; it's not used rherveille 6217d 00h /
60 Added missing semicolons ';' on endif rherveille 6393d 21h /
59 fixed short scl high pulse after clock stretch rherveille 6398d 23h /
58 fixed (n)ack generation rherveille 6431d 00h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 6431d 00h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 6983d 22h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 6985d 00h /
54 Fixed scl, sda delay. rherveille 6985d 00h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7280d 22h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7280d 22h /
51 Fixed simulation issue when writing to CR register rherveille 7334d 23h /
50 *** empty log message *** rherveille 7349d 18h /
49 Added testbench rherveille 7349d 18h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7351d 02h /
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7359d 22h /
46 Fixed slave address MSB='1' bug rherveille 7434d 22h /
45 Added slave address configurability rherveille 7434d 22h /
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7520d 01h /
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7520d 01h /
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7529d 23h /
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7529d 23h /
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7529d 23h /
39 Forgot an 'end if' :-/ rherveille 7549d 19h /

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