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Rev Log message Author Age Path
73 Fixed double wishbone write in a single access rherveille 5305d 23h /
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 5305d 23h /
71 Fixed double wishbone write in a single access rherveille 5305d 23h /
70 Added old uploaded documents to new repository. root 5614d 02h /
69 Added old uploaded documents to new repository. root 5614d 17h /
68 New directory structure. root 5614d 17h /
67 Fixed slave_wait clocked event syntax rherveille 5647d 19h /
66 Fixed type iscl_oen instead of scl_oen rherveille 5662d 19h /
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5663d 05h /
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 5663d 05h /
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 5663d 05h /
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 5663d 19h /
61 Removed synopsys link; it's not used rherveille 6318d 06h /
60 Added missing semicolons ';' on endif rherveille 6495d 03h /
59 fixed short scl high pulse after clock stretch rherveille 6500d 05h /
58 fixed (n)ack generation rherveille 6532d 06h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 6532d 06h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 7085d 04h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 7086d 06h /
54 Fixed scl, sda delay. rherveille 7086d 06h /

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