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Rev Log message Author Age Path
75 Fixed sSDA generation rherveille 4379d 07h /
74 Added SCL/SDA line filter rherveille 4518d 04h /
73 Fixed double wishbone write in a single access rherveille 4518d 04h /
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 4518d 04h /
71 Fixed double wishbone write in a single access rherveille 4518d 04h /
70 Added old uploaded documents to new repository. root 4826d 07h /
69 Added old uploaded documents to new repository. root 4826d 22h /
68 New directory structure. root 4826d 22h /
67 Fixed slave_wait clocked event syntax rherveille 4860d 00h /
66 Fixed type iscl_oen instead of scl_oen rherveille 4875d 00h /
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 4875d 10h /
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 4875d 10h /
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 4875d 10h /
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 4876d 00h /
61 Removed synopsys link; it's not used rherveille 5530d 11h /
60 Added missing semicolons ';' on endif rherveille 5707d 08h /
59 fixed short scl high pulse after clock stretch rherveille 5712d 10h /
58 fixed (n)ack generation rherveille 5744d 11h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 5744d 11h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 6297d 09h /

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