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[/] [.] - Rev 68

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Rev	Log message	Author	Age	Path
68	New directory structure.	root	5528d 12h	/.
67	Fixed slave_wait clocked event syntax	rherveille	5561d 14h	/.
66	Fixed type iscl_oen instead of scl_oen	rherveille	5576d 13h	/.
65	Changed wb_adr_i from unsigned to std_logic_vector	rherveille	5576d 23h	/.
64	Added SCL clock synchronization logic Fixed slave_wait signal generation	rherveille	5576d 23h	/.
63	Added clock synchronization logic Fixed slave_wait signal	rherveille	5577d 00h	/.
62	Fixed synopsys miss spell (synopsis) Fixed cr[0] register width Fixed ! usage instead of ~ Fixed bit controller parameter width to 18bits	rherveille	5577d 14h	/.
61	Removed synopsys link; it's not used	rherveille	6232d 01h	/.
60	Added missing semicolons ';' on endif	rherveille	6408d 22h	/.
59	fixed short scl high pulse after clock stretch	rherveille	6413d 23h	/.
58	fixed (n)ack generation	rherveille	6446d 01h	/.
57	fixed short scl high pulse after clock stretch fixed slave model not returning correct '(n)ack' signal	rherveille	6446d 01h	/.
56	Fixed Tsu:sta timing check. Added Thd:sta timing check.	rherveille	6998d 22h	/.
55	Fixed register overwrite issue. Removed full_case pragma, replaced it by a default statement.	rherveille	7000d 01h	/.
54	Fixed scl, sda delay.	rherveille	7000d 01h	/.
53	Fixed previous fix :) Made a variable vs signal mistake.	rherveille	7295d 22h	/.
52	Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.	rherveille	7295d 23h	/.
51	Fixed simulation issue when writing to CR register	rherveille	7350d 00h	/.
50	* empty log message *	rherveille	7364d 18h	/.
49	Added testbench	rherveille	7364d 18h	/.

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[/] [.] - Rev 68

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