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Rev Log message Author Age Path
68 New directory structure. root 5543d 00h /.
67 Fixed slave_wait clocked event syntax rherveille 5576d 02h /.
66 Fixed type iscl_oen instead of scl_oen rherveille 5591d 02h /.
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5591d 12h /.
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation		 rherveille 5591d 12h /.
63 Added clock synchronization logic
Fixed slave_wait signal		 rherveille 5591d 12h /.
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits		 rherveille 5592d 02h /.
61 Removed synopsys link; it's not used rherveille 6246d 13h /.
60 Added missing semicolons ';' on endif rherveille 6423d 10h /.
59 fixed short scl high pulse after clock stretch rherveille 6428d 12h /.
58 fixed (n)ack generation rherveille 6460d 13h /.
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal		 rherveille 6460d 13h /.
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.		 rherveille 7013d 11h /.
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.		 rherveille 7014d 13h /.
54 Fixed scl, sda delay. rherveille 7014d 13h /.
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7310d 10h /.
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7310d 11h /.
51 Fixed simulation issue when writing to CR register rherveille 7364d 12h /.
50 *** empty log message *** rherveille 7379d 07h /.
49 Added testbench rherveille 7379d 07h /.
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7380d 14h /.
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7389d 11h /.
46 Fixed slave address MSB='1' bug rherveille 7464d 11h /.
45 Added slave address configurability rherveille 7464d 11h /.
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7549d 14h /.
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7549d 14h /.
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7559d 12h /.
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7559d 12h /.
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7559d 12h /.
39 Forgot an 'end if' :-/ rherveille 7579d 08h /.

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