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[/] [i2c/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 70

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Rev Log message Author Age Path
68 New directory structure. root 5531d 00h /i2c/tags/asyst_2/rtl/verilog/
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7547d 12h /i2c/tags/asyst_2/rtl/verilog/
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7547d 12h /i2c/tags/asyst_2/rtl/verilog/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7570d 15h /i2c/tags/asyst_2/rtl/verilog/
36 Fixed cmd_ack generation item (no bug). rherveille 7722d 08h /i2c/tags/asyst_2/rtl/verilog/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7755d 22h /i2c/tags/asyst_2/rtl/verilog/
33 Fixed a bug in the Command Register declaration. rherveille 7782d 05h /i2c/tags/asyst_2/rtl/verilog/
30 Small code simplifications rherveille 7796d 06h /i2c/tags/asyst_2/rtl/verilog/
29 Core is now a Multimaster I2C controller rherveille 7796d 07h /i2c/tags/asyst_2/rtl/verilog/
27 Cleaned up code rherveille 7822d 00h /i2c/tags/asyst_2/rtl/verilog/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7853d 04h /i2c/tags/asyst_2/rtl/verilog/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7990d 15h /i2c/tags/asyst_2/rtl/verilog/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8207d 11h /i2c/tags/asyst_2/rtl/verilog/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8212d 10h /i2c/tags/asyst_2/rtl/verilog/
13 Fixed some synthesis warnings. rherveille 8223d 14h /i2c/tags/asyst_2/rtl/verilog/
11 Changed RST_LVL define to parameter. rherveille 8232d 13h /i2c/tags/asyst_2/rtl/verilog/
10 Created new directory structure.
Added Verilog version.		 rherveille 8254d 10h /i2c/tags/asyst_2/rtl/verilog/

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