URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_3/] - Rev 15

Rev	Log message	Author	Age	Path
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8221d 20h	/i2c/tags/asyst_3/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8221d 20h	/i2c/tags/asyst_3/
13	Fixed some synthesis warnings.	rherveille	8233d 00h	/i2c/tags/asyst_3/
12	no message	rherveille	8238d 16h	/i2c/tags/asyst_3/
11	Changed RST_LVL define to parameter.	rherveille	8241d 23h	/i2c/tags/asyst_3/
10	Created new directory structure. Added Verilog version.	rherveille	8263d 20h	/i2c/tags/asyst_3/
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8333d 15h	/i2c/tags/asyst_3/
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8333d 15h	/i2c/tags/asyst_3/
7	added some remarks, fixed some sensitivity lists	rherveille	8402d 18h	/i2c/tags/asyst_3/
6	fixed typo txt -> txr	rherveille	8406d 22h	/i2c/tags/asyst_3/
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8413d 20h	/i2c/tags/asyst_3/
4	WISHBONE I2C Master Core: initial release	rherveille	8465d 23h	/i2c/tags/asyst_3/
2	initial release	rherveille	8527d 22h	/i2c/tags/asyst_3/
1	Standard project directories initialized by cvs2svn.		8527d 22h	/i2c/tags/asyst_3/