OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_3/] - Rev 38

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7600d 16h /i2c/tags/asyst_3/
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7637d 08h /i2c/tags/asyst_3/
36 Fixed cmd_ack generation item (no bug). rherveille 7752d 09h /i2c/tags/asyst_3/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7785d 23h /i2c/tags/asyst_3/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7789d 21h /i2c/tags/asyst_3/
33 Fixed a bug in the Command Register declaration. rherveille 7812d 06h /i2c/tags/asyst_3/
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7822d 06h /i2c/tags/asyst_3/
31 Core is now a Multimaster I2C controller. rherveille 7826d 07h /i2c/tags/asyst_3/
30 Small code simplifications rherveille 7826d 07h /i2c/tags/asyst_3/
29 Core is now a Multimaster I2C controller rherveille 7826d 08h /i2c/tags/asyst_3/
28 *** empty log message *** rherveille 7852d 01h /i2c/tags/asyst_3/
27 Cleaned up code rherveille 7852d 01h /i2c/tags/asyst_3/
26 *** empty log message *** rherveille 7855d 09h /i2c/tags/asyst_3/
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7883d 05h /i2c/tags/asyst_3/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7883d 05h /i2c/tags/asyst_3/
23 *** empty log message *** rherveille 8010d 10h /i2c/tags/asyst_3/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8020d 15h /i2c/tags/asyst_3/
21 no message rherveille 8106d 16h /i2c/tags/asyst_3/
20 Added Appendix A rherveille 8106d 16h /i2c/tags/asyst_3/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8110d 13h /i2c/tags/asyst_3/
18 no message rherveille 8137d 08h /i2c/tags/asyst_3/
17 C-include file.
Initial release		 rherveille 8225d 13h /i2c/tags/asyst_3/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8237d 12h /i2c/tags/asyst_3/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8242d 11h /i2c/tags/asyst_3/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8242d 11h /i2c/tags/asyst_3/
13 Fixed some synthesis warnings. rherveille 8253d 15h /i2c/tags/asyst_3/
12 no message rherveille 8259d 07h /i2c/tags/asyst_3/
11 Changed RST_LVL define to parameter. rherveille 8262d 14h /i2c/tags/asyst_3/
10 Created new directory structure.
Added Verilog version.		 rherveille 8284d 11h /i2c/tags/asyst_3/
9 Created directory structure (documentation, vhdl, verilog) rherveille 8354d 06h /i2c/tags/asyst_3/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.