URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_3/] - Rev 69

Rev	Log message	Author	Age	Path
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	7985d 21h	/i2c/tags/asyst_3/
21	no message	rherveille	8071d 21h	/i2c/tags/asyst_3/
20	Added Appendix A	rherveille	8071d 21h	/i2c/tags/asyst_3/
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8075d 18h	/i2c/tags/asyst_3/
18	no message	rherveille	8102d 14h	/i2c/tags/asyst_3/
17	C-include file. Initial release	rherveille	8190d 18h	/i2c/tags/asyst_3/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8202d 17h	/i2c/tags/asyst_3/
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8207d 16h	/i2c/tags/asyst_3/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8207d 16h	/i2c/tags/asyst_3/
13	Fixed some synthesis warnings.	rherveille	8218d 20h	/i2c/tags/asyst_3/