URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_3/] [rtl/] - Rev 31

Rev	Log message	Author	Age	Path
31	Core is now a Multimaster I2C controller.	rherveille	7797d 02h	/i2c/tags/asyst_3/rtl/
30	Small code simplifications	rherveille	7797d 02h	/i2c/tags/asyst_3/rtl/
29	Core is now a Multimaster I2C controller	rherveille	7797d 03h	/i2c/tags/asyst_3/rtl/
28	* empty log message *	rherveille	7822d 19h	/i2c/tags/asyst_3/rtl/
27	Cleaned up code	rherveille	7822d 19h	/i2c/tags/asyst_3/rtl/
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7853d 23h	/i2c/tags/asyst_3/rtl/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	7991d 10h	/i2c/tags/asyst_3/rtl/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8208d 07h	/i2c/tags/asyst_3/rtl/
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8213d 06h	/i2c/tags/asyst_3/rtl/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8213d 06h	/i2c/tags/asyst_3/rtl/
13	Fixed some synthesis warnings.	rherveille	8224d 10h	/i2c/tags/asyst_3/rtl/
11	Changed RST_LVL define to parameter.	rherveille	8233d 09h	/i2c/tags/asyst_3/rtl/
10	Created new directory structure. Added Verilog version.	rherveille	8255d 05h	/i2c/tags/asyst_3/rtl/