URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_3/] [rtl/] - Rev 33

Rev	Log message	Author	Age	Path
33	Fixed a bug in the Command Register declaration.	rherveille	7779d 08h	/i2c/tags/asyst_3/rtl/
31	Core is now a Multimaster I2C controller.	rherveille	7793d 09h	/i2c/tags/asyst_3/rtl/
30	Small code simplifications	rherveille	7793d 09h	/i2c/tags/asyst_3/rtl/
29	Core is now a Multimaster I2C controller	rherveille	7793d 10h	/i2c/tags/asyst_3/rtl/
28	* empty log message *	rherveille	7819d 02h	/i2c/tags/asyst_3/rtl/
27	Cleaned up code	rherveille	7819d 02h	/i2c/tags/asyst_3/rtl/
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7850d 07h	/i2c/tags/asyst_3/rtl/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	7987d 17h	/i2c/tags/asyst_3/rtl/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8204d 14h	/i2c/tags/asyst_3/rtl/
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8209d 13h	/i2c/tags/asyst_3/rtl/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8209d 13h	/i2c/tags/asyst_3/rtl/
13	Fixed some synthesis warnings.	rherveille	8220d 17h	/i2c/tags/asyst_3/rtl/
11	Changed RST_LVL define to parameter.	rherveille	8229d 16h	/i2c/tags/asyst_3/rtl/
10	Created new directory structure. Added Verilog version.	rherveille	8251d 13h	/i2c/tags/asyst_3/rtl/