URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_3/] [rtl/] [verilog/] - Rev 35

Rev	Log message	Author	Age	Path
35	Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.	rherveille	7783d 11h	/i2c/tags/asyst_3/rtl/verilog/
33	Fixed a bug in the Command Register declaration.	rherveille	7809d 19h	/i2c/tags/asyst_3/rtl/verilog/
30	Small code simplifications	rherveille	7823d 19h	/i2c/tags/asyst_3/rtl/verilog/
29	Core is now a Multimaster I2C controller	rherveille	7823d 21h	/i2c/tags/asyst_3/rtl/verilog/
27	Cleaned up code	rherveille	7849d 13h	/i2c/tags/asyst_3/rtl/verilog/
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7880d 17h	/i2c/tags/asyst_3/rtl/verilog/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8018d 04h	/i2c/tags/asyst_3/rtl/verilog/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8235d 01h	/i2c/tags/asyst_3/rtl/verilog/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8240d 00h	/i2c/tags/asyst_3/rtl/verilog/
13	Fixed some synthesis warnings.	rherveille	8251d 04h	/i2c/tags/asyst_3/rtl/verilog/
11	Changed RST_LVL define to parameter.	rherveille	8260d 03h	/i2c/tags/asyst_3/rtl/verilog/
10	Created new directory structure. Added Verilog version.	rherveille	8281d 23h	/i2c/tags/asyst_3/rtl/verilog/