URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_3/] [rtl/] [verilog/] [i2c_master_byte_ctrl.v] - Rev 69

Rev	Log message	Author	Age	Path
68	New directory structure.	root	5532d 09h	/i2c/tags/asyst_3/rtl/verilog/i2c_master_byte_ctrl.v
42	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		7548d 20h	/i2c/tags/asyst_3/rtl/verilog/i2c_master_byte_ctrl.v
38	Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. Fixed a potential bug in the byte controller's host-acknowledge generation.	rherveille	7572d 00h	/i2c/tags/asyst_3/rtl/verilog/i2c_master_byte_ctrl.v
29	Core is now a Multimaster I2C controller	rherveille	7797d 16h	/i2c/tags/asyst_3/rtl/verilog/i2c_master_byte_ctrl.v
27	Cleaned up code	rherveille	7823d 09h	/i2c/tags/asyst_3/rtl/verilog/i2c_master_byte_ctrl.v
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8213d 19h	/i2c/tags/asyst_3/rtl/verilog/i2c_master_byte_ctrl.v
13	Fixed some synthesis warnings.	rherveille	8224d 23h	/i2c/tags/asyst_3/rtl/verilog/i2c_master_byte_ctrl.v
10	Created new directory structure. Added Verilog version.	rherveille	8255d 19h	/i2c/tags/asyst_3/rtl/verilog/i2c_master_byte_ctrl.v