URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [rel_1/] - Rev 12

Rev	Log message	Author	Age	Path
12	no message	rherveille	8238d 14h	/i2c/tags/rel_1/
11	Changed RST_LVL define to parameter.	rherveille	8241d 21h	/i2c/tags/rel_1/
10	Created new directory structure. Added Verilog version.	rherveille	8263d 18h	/i2c/tags/rel_1/
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8333d 13h	/i2c/tags/rel_1/
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8333d 13h	/i2c/tags/rel_1/
7	added some remarks, fixed some sensitivity lists	rherveille	8402d 15h	/i2c/tags/rel_1/
6	fixed typo txt -> txr	rherveille	8406d 19h	/i2c/tags/rel_1/
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8413d 17h	/i2c/tags/rel_1/
4	WISHBONE I2C Master Core: initial release	rherveille	8465d 20h	/i2c/tags/rel_1/
2	initial release	rherveille	8527d 20h	/i2c/tags/rel_1/
1	Standard project directories initialized by cvs2svn.		8527d 20h	/i2c/tags/rel_1/