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[/] [i2c/] [tags/] [rel_1/] - Rev 22

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Rev Log message Author Age Path
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7986d 05h /i2c/tags/rel_1/
21 no message rherveille 8072d 05h /i2c/tags/rel_1/
20 Added Appendix A rherveille 8072d 05h /i2c/tags/rel_1/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8076d 02h /i2c/tags/rel_1/
18 no message rherveille 8102d 22h /i2c/tags/rel_1/
17 C-include file.
Initial release		 rherveille 8191d 02h /i2c/tags/rel_1/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8203d 01h /i2c/tags/rel_1/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8208d 00h /i2c/tags/rel_1/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8208d 00h /i2c/tags/rel_1/
13 Fixed some synthesis warnings. rherveille 8219d 04h /i2c/tags/rel_1/
12 no message rherveille 8224d 20h /i2c/tags/rel_1/
11 Changed RST_LVL define to parameter. rherveille 8228d 03h /i2c/tags/rel_1/
10 Created new directory structure.
Added Verilog version.		 rherveille 8250d 00h /i2c/tags/rel_1/
9 Created directory structure (documentation, vhdl, verilog) rherveille 8319d 19h /i2c/tags/rel_1/
8 Created directory structure (documentation, vhdl, verilog) rherveille 8319d 19h /i2c/tags/rel_1/
7 added some remarks, fixed some sensitivity lists rherveille 8388d 22h /i2c/tags/rel_1/
6 fixed typo txt -> txr rherveille 8393d 01h /i2c/tags/rel_1/
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8400d 00h /i2c/tags/rel_1/
4 WISHBONE I2C Master Core: initial release rherveille 8452d 03h /i2c/tags/rel_1/
2 initial release rherveille 8514d 02h /i2c/tags/rel_1/

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