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[/] [i2c/] [tags/] [rel_1/] - Rev 68


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Rev Log message Author Age Path
23 *** empty log message *** rherveille 7651d 17h /i2c/tags/rel_1/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7661d 22h /i2c/tags/rel_1/
21 no message rherveille 7747d 23h /i2c/tags/rel_1/
20 Added Appendix A rherveille 7747d 23h /i2c/tags/rel_1/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 7751d 19h /i2c/tags/rel_1/
18 no message rherveille 7778d 15h /i2c/tags/rel_1/
17 C-include file.
Initial release
rherveille 7866d 20h /i2c/tags/rel_1/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 7878d 19h /i2c/tags/rel_1/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 7883d 18h /i2c/tags/rel_1/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 7883d 18h /i2c/tags/rel_1/

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