OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [rel_1/] - Rev 75

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
23 *** empty log message *** rherveille 7982d 07h /i2c/tags/rel_1/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7992d 12h /i2c/tags/rel_1/
21 no message rherveille 8078d 13h /i2c/tags/rel_1/
20 Added Appendix A rherveille 8078d 13h /i2c/tags/rel_1/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8082d 10h /i2c/tags/rel_1/
18 no message rherveille 8109d 05h /i2c/tags/rel_1/
17 C-include file.
Initial release		 rherveille 8197d 10h /i2c/tags/rel_1/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8209d 09h /i2c/tags/rel_1/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8214d 08h /i2c/tags/rel_1/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8214d 08h /i2c/tags/rel_1/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.