URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [rel_1/] [bench/] [verilog/] - Rev 70

Rev	Log message	Author	Age	Path
68	New directory structure.	root	5533d 11h	/i2c/tags/rel_1/bench/verilog/
44	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7540d 01h	/i2c/tags/rel_1/bench/verilog/
43	Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.	rherveille	7540d 01h	/i2c/tags/rel_1/bench/verilog/
25	Added timing tests to i2c_model. Updated testbench.	rherveille	7855d 16h	/i2c/tags/rel_1/bench/verilog/
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8082d 23h	/i2c/tags/rel_1/bench/verilog/
10	Created new directory structure. Added Verilog version.	rherveille	8256d 21h	/i2c/tags/rel_1/bench/verilog/