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[/] [i2c/] [tags/] [rel_1/] [rtl/] [verilog/] - Rev 68

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Rev Log message Author Age Path
68 New directory structure. root 5531d 21h /i2c/tags/rel_1/rtl/verilog/
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7538d 11h /i2c/tags/rel_1/rtl/verilog/
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7548d 09h /i2c/tags/rel_1/rtl/verilog/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7571d 13h /i2c/tags/rel_1/rtl/verilog/
36 Fixed cmd_ack generation item (no bug). rherveille 7723d 05h /i2c/tags/rel_1/rtl/verilog/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7756d 19h /i2c/tags/rel_1/rtl/verilog/
33 Fixed a bug in the Command Register declaration. rherveille 7783d 03h /i2c/tags/rel_1/rtl/verilog/
30 Small code simplifications rherveille 7797d 03h /i2c/tags/rel_1/rtl/verilog/
29 Core is now a Multimaster I2C controller rherveille 7797d 04h /i2c/tags/rel_1/rtl/verilog/
27 Cleaned up code rherveille 7822d 21h /i2c/tags/rel_1/rtl/verilog/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7854d 01h /i2c/tags/rel_1/rtl/verilog/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7991d 12h /i2c/tags/rel_1/rtl/verilog/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8208d 09h /i2c/tags/rel_1/rtl/verilog/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8213d 08h /i2c/tags/rel_1/rtl/verilog/
13 Fixed some synthesis warnings. rherveille 8224d 12h /i2c/tags/rel_1/rtl/verilog/
11 Changed RST_LVL define to parameter. rherveille 8233d 11h /i2c/tags/rel_1/rtl/verilog/
10 Created new directory structure.
Added Verilog version.		 rherveille 8255d 07h /i2c/tags/rel_1/rtl/verilog/

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