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Subversion Repositories i2c

[/] [i2c/] [tags/] [rel_1/] [rtl/] [verilog/] [i2c_master_top.v] - Rev 68

Rev	Log message	Author	Age	Path
68	New directory structure.	root	5552d 16h	/i2c/tags/rel_1/rtl/verilog/i2c_master_top.v
44	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7559d 06h	/i2c/tags/rel_1/rtl/verilog/i2c_master_top.v
40	Fix a blocking vs. non-blocking error in the wb_dat output mux.	rherveille	7569d 04h	/i2c/tags/rel_1/rtl/verilog/i2c_master_top.v
33	Fixed a bug in the Command Register declaration.	rherveille	7803d 22h	/i2c/tags/rel_1/rtl/verilog/i2c_master_top.v
30	Small code simplifications	rherveille	7817d 22h	/i2c/tags/rel_1/rtl/verilog/i2c_master_top.v
29	Core is now a Multimaster I2C controller	rherveille	7817d 23h	/i2c/tags/rel_1/rtl/verilog/i2c_master_top.v
27	Cleaned up code	rherveille	7843d 16h	/i2c/tags/rel_1/rtl/verilog/i2c_master_top.v
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8229d 03h	/i2c/tags/rel_1/rtl/verilog/i2c_master_top.v
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8234d 02h	/i2c/tags/rel_1/rtl/verilog/i2c_master_top.v
13	Fixed some synthesis warnings.	rherveille	8245d 06h	/i2c/tags/rel_1/rtl/verilog/i2c_master_top.v
11	Changed RST_LVL define to parameter.	rherveille	8254d 05h	/i2c/tags/rel_1/rtl/verilog/i2c_master_top.v
10	Created new directory structure. Added Verilog version.	rherveille	8276d 02h	/i2c/tags/rel_1/rtl/verilog/i2c_master_top.v