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[/] [i2c/] [tags/] [rel_1/] [rtl/] [vhdl/] - Rev 68

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Rev Log message Author Age Path
68 New directory structure. root 5531d 22h /i2c/tags/rel_1/rtl/vhdl/
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7538d 12h /i2c/tags/rel_1/rtl/vhdl/
39 Forgot an 'end if' :-/ rherveille 7568d 05h /i2c/tags/rel_1/rtl/vhdl/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7571d 13h /i2c/tags/rel_1/rtl/vhdl/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7756d 20h /i2c/tags/rel_1/rtl/vhdl/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7760d 18h /i2c/tags/rel_1/rtl/vhdl/
31 Core is now a Multimaster I2C controller. rherveille 7797d 04h /i2c/tags/rel_1/rtl/vhdl/
28 *** empty log message *** rherveille 7822d 22h /i2c/tags/rel_1/rtl/vhdl/
27 Cleaned up code rherveille 7822d 22h /i2c/tags/rel_1/rtl/vhdl/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7854d 02h /i2c/tags/rel_1/rtl/vhdl/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7991d 13h /i2c/tags/rel_1/rtl/vhdl/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8208d 09h /i2c/tags/rel_1/rtl/vhdl/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8213d 08h /i2c/tags/rel_1/rtl/vhdl/
10 Created new directory structure.
Added Verilog version.		 rherveille 8255d 08h /i2c/tags/rel_1/rtl/vhdl/

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