URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [rel_1] - Rev 14

Rev	Log message	Author	Age	Path
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8231d 01h	/i2c/tags/rel_1
13	Fixed some synthesis warnings.	rherveille	8242d 05h	/i2c/tags/rel_1
12	no message	rherveille	8247d 20h	/i2c/tags/rel_1
11	Changed RST_LVL define to parameter.	rherveille	8251d 04h	/i2c/tags/rel_1
10	Created new directory structure. Added Verilog version.	rherveille	8273d 00h	/i2c/tags/rel_1
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8342d 19h	/i2c/tags/rel_1
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8342d 19h	/i2c/tags/rel_1
7	added some remarks, fixed some sensitivity lists	rherveille	8411d 22h	/i2c/tags/rel_1
6	fixed typo txt -> txr	rherveille	8416d 02h	/i2c/tags/rel_1
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8423d 00h	/i2c/tags/rel_1
4	WISHBONE I2C Master Core: initial release	rherveille	8475d 03h	/i2c/tags/rel_1
2	initial release	rherveille	8537d 02h	/i2c/tags/rel_1
1	Standard project directories initialized by cvs2svn.		8537d 02h	/i2c/tags/rel_1