URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [rel_1] - Rev 18

Rev	Log message	Author	Age	Path
18	no message	rherveille	8124d 08h	/i2c/tags/rel_1
17	C-include file. Initial release	rherveille	8212d 12h	/i2c/tags/rel_1
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8224d 12h	/i2c/tags/rel_1
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8229d 10h	/i2c/tags/rel_1
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8229d 10h	/i2c/tags/rel_1
13	Fixed some synthesis warnings.	rherveille	8240d 14h	/i2c/tags/rel_1
12	no message	rherveille	8246d 06h	/i2c/tags/rel_1
11	Changed RST_LVL define to parameter.	rherveille	8249d 13h	/i2c/tags/rel_1
10	Created new directory structure. Added Verilog version.	rherveille	8271d 10h	/i2c/tags/rel_1
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8341d 05h	/i2c/tags/rel_1
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8341d 05h	/i2c/tags/rel_1
7	added some remarks, fixed some sensitivity lists	rherveille	8410d 08h	/i2c/tags/rel_1
6	fixed typo txt -> txr	rherveille	8414d 12h	/i2c/tags/rel_1
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8421d 10h	/i2c/tags/rel_1
4	WISHBONE I2C Master Core: initial release	rherveille	8473d 13h	/i2c/tags/rel_1
2	initial release	rherveille	8535d 12h	/i2c/tags/rel_1
1	Standard project directories initialized by cvs2svn.		8535d 12h	/i2c/tags/rel_1