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URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] - Rev 76

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Rev Log message Author Age Path
76 Updated filter_cnt generation rherveille 3472d 06h /i2c/trunk/
75 Fixed sSDA generation rherveille 3478d 02h /i2c/trunk/
74 Added SCL/SDA line filter rherveille 3616d 23h /i2c/trunk/
73 Fixed double wishbone write in a single access rherveille 3616d 23h /i2c/trunk/
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 3616d 23h /i2c/trunk/
71 Fixed double wishbone write in a single access rherveille 3616d 23h /i2c/trunk/
68 New directory structure. root 3925d 17h /i2c/trunk/
67 Fixed slave_wait clocked event syntax rherveille 3958d 19h /trunk/
66 Fixed type iscl_oen instead of scl_oen rherveille 3973d 19h /trunk/
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 3974d 05h /trunk/
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 3974d 05h /trunk/
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 3974d 05h /trunk/
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 3974d 19h /trunk/
61 Removed synopsys link; it's not used rherveille 4629d 06h /trunk/
60 Added missing semicolons ';' on endif rherveille 4806d 03h /trunk/
59 fixed short scl high pulse after clock stretch rherveille 4811d 05h /trunk/
58 fixed (n)ack generation rherveille 4843d 06h /trunk/
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 4843d 06h /trunk/
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 5396d 04h /trunk/
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 5397d 06h /trunk/

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