URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] - Rev 15

Rev	Log message	Author	Age	Path
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8208d 05h	/i2c/trunk/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8208d 05h	/i2c/trunk/
13	Fixed some synthesis warnings.	rherveille	8219d 09h	/i2c/trunk/
12	no message	rherveille	8225d 01h	/i2c/trunk/
11	Changed RST_LVL define to parameter.	rherveille	8228d 08h	/i2c/trunk/
10	Created new directory structure. Added Verilog version.	rherveille	8250d 05h	/i2c/trunk/
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8320d 00h	/i2c/trunk/
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8320d 00h	/i2c/trunk/
7	added some remarks, fixed some sensitivity lists	rherveille	8389d 03h	/i2c/trunk/
6	fixed typo txt -> txr	rherveille	8393d 06h	/i2c/trunk/
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8400d 05h	/i2c/trunk/
4	WISHBONE I2C Master Core: initial release	rherveille	8452d 08h	/i2c/trunk/
2	initial release	rherveille	8514d 07h	/i2c/trunk/
1	Standard project directories initialized by cvs2svn.		8514d 07h	/i2c/trunk/