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Rev Log message Author Age Path
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 7547d 04h /i2c/trunk/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 7547d 04h /i2c/trunk/
13 Fixed some synthesis warnings. rherveille 7558d 08h /i2c/trunk/
12 no message rherveille 7564d 00h /i2c/trunk/
11 Changed RST_LVL define to parameter. rherveille 7567d 07h /i2c/trunk/
10 Created new directory structure.
Added Verilog version.
rherveille 7589d 04h /i2c/trunk/
9 Created directory structure (documentation, vhdl, verilog) rherveille 7658d 23h /i2c/trunk/
8 Created directory structure (documentation, vhdl, verilog) rherveille 7658d 23h /i2c/trunk/
7 added some remarks, fixed some sensitivity lists rherveille 7728d 02h /i2c/trunk/
6 fixed typo txt -> txr rherveille 7732d 05h /i2c/trunk/
5 fixed an incomplete sensitivity list on assign_dato process rherveille 7739d 04h /i2c/trunk/
4 WISHBONE I2C Master Core: initial release rherveille 7791d 07h /i2c/trunk/
2 initial release rherveille 7853d 06h /i2c/trunk/
1 Standard project directories initialized by cvs2svn. 7853d 06h /i2c/trunk/

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