URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] - Rev 18

Rev	Log message	Author	Age	Path
18	no message	rherveille	8116d 22h	/i2c/trunk/
17	C-include file. Initial release	rherveille	8205d 02h	/i2c/trunk/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8217d 01h	/i2c/trunk/
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8222d 00h	/i2c/trunk/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8222d 00h	/i2c/trunk/
13	Fixed some synthesis warnings.	rherveille	8233d 04h	/i2c/trunk/
12	no message	rherveille	8238d 20h	/i2c/trunk/
11	Changed RST_LVL define to parameter.	rherveille	8242d 03h	/i2c/trunk/
10	Created new directory structure. Added Verilog version.	rherveille	8264d 00h	/i2c/trunk/
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8333d 19h	/i2c/trunk/
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8333d 19h	/i2c/trunk/
7	added some remarks, fixed some sensitivity lists	rherveille	8402d 22h	/i2c/trunk/
6	fixed typo txt -> txr	rherveille	8407d 01h	/i2c/trunk/
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8414d 00h	/i2c/trunk/
4	WISHBONE I2C Master Core: initial release	rherveille	8466d 03h	/i2c/trunk/
2	initial release	rherveille	8528d 02h	/i2c/trunk/
1	Standard project directories initialized by cvs2svn.		8528d 02h	/i2c/trunk/