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[/] [i2c/] [trunk/] - Rev 20

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Rev Log message Author Age Path
20 Added Appendix A rherveille 8078d 07h /i2c/trunk/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8082d 04h /i2c/trunk/
18 no message rherveille 8108d 23h /i2c/trunk/
17 C-include file.
Initial release		 rherveille 8197d 04h /i2c/trunk/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8209d 03h /i2c/trunk/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8214d 02h /i2c/trunk/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8214d 02h /i2c/trunk/
13 Fixed some synthesis warnings. rherveille 8225d 06h /i2c/trunk/
12 no message rherveille 8230d 22h /i2c/trunk/
11 Changed RST_LVL define to parameter. rherveille 8234d 05h /i2c/trunk/
10 Created new directory structure.
Added Verilog version.		 rherveille 8256d 02h /i2c/trunk/
9 Created directory structure (documentation, vhdl, verilog) rherveille 8325d 21h /i2c/trunk/
8 Created directory structure (documentation, vhdl, verilog) rherveille 8325d 21h /i2c/trunk/
7 added some remarks, fixed some sensitivity lists rherveille 8394d 23h /i2c/trunk/
6 fixed typo txt -> txr rherveille 8399d 03h /i2c/trunk/
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8406d 01h /i2c/trunk/
4 WISHBONE I2C Master Core: initial release rherveille 8458d 04h /i2c/trunk/
2 initial release rherveille 8520d 04h /i2c/trunk/
1 Standard project directories initialized by cvs2svn. 8520d 04h /i2c/trunk/

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