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[/] [i2c/] [trunk/] - Rev 24

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Rev Log message Author Age Path
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7854d 15h /i2c/trunk/
23 *** empty log message *** rherveille 7981d 20h /i2c/trunk/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7992d 01h /i2c/trunk/
21 no message rherveille 8078d 02h /i2c/trunk/
20 Added Appendix A rherveille 8078d 02h /i2c/trunk/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8081d 22h /i2c/trunk/
18 no message rherveille 8108d 18h /i2c/trunk/
17 C-include file.
Initial release		 rherveille 8196d 23h /i2c/trunk/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8208d 22h /i2c/trunk/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8213d 21h /i2c/trunk/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8213d 21h /i2c/trunk/
13 Fixed some synthesis warnings. rherveille 8225d 01h /i2c/trunk/
12 no message rherveille 8230d 16h /i2c/trunk/
11 Changed RST_LVL define to parameter. rherveille 8234d 00h /i2c/trunk/
10 Created new directory structure.
Added Verilog version.		 rherveille 8255d 20h /i2c/trunk/
9 Created directory structure (documentation, vhdl, verilog) rherveille 8325d 16h /i2c/trunk/
8 Created directory structure (documentation, vhdl, verilog) rherveille 8325d 16h /i2c/trunk/
7 added some remarks, fixed some sensitivity lists rherveille 8394d 18h /i2c/trunk/
6 fixed typo txt -> txr rherveille 8398d 22h /i2c/trunk/
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8405d 20h /i2c/trunk/
4 WISHBONE I2C Master Core: initial release rherveille 8457d 23h /i2c/trunk/
2 initial release rherveille 8519d 23h /i2c/trunk/
1 Standard project directories initialized by cvs2svn. 8519d 23h /i2c/trunk/

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