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[/] [i2c/] [trunk/] - Rev 30

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Rev Log message Author Age Path
30 Small code simplifications rherveille 7961d 00h /i2c/trunk/
29 Core is now a Multimaster I2C controller rherveille 7961d 01h /i2c/trunk/
28 *** empty log message *** rherveille 7986d 18h /i2c/trunk/
27 Cleaned up code rherveille 7986d 18h /i2c/trunk/
26 *** empty log message *** rherveille 7990d 02h /i2c/trunk/
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 8017d 22h /i2c/trunk/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 8017d 22h /i2c/trunk/
23 *** empty log message *** rherveille 8145d 03h /i2c/trunk/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8155d 09h /i2c/trunk/
21 no message rherveille 8241d 09h /i2c/trunk/
20 Added Appendix A rherveille 8241d 09h /i2c/trunk/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 8245d 06h /i2c/trunk/
18 no message rherveille 8272d 02h /i2c/trunk/
17 C-include file.
Initial release
rherveille 8360d 06h /i2c/trunk/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8372d 05h /i2c/trunk/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 8377d 04h /i2c/trunk/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 8377d 04h /i2c/trunk/
13 Fixed some synthesis warnings. rherveille 8388d 08h /i2c/trunk/
12 no message rherveille 8394d 00h /i2c/trunk/
11 Changed RST_LVL define to parameter. rherveille 8397d 07h /i2c/trunk/

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