OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] - Rev 30

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
30 Small code simplifications rherveille 7815d 12h /i2c/trunk/
29 Core is now a Multimaster I2C controller rherveille 7815d 13h /i2c/trunk/
28 *** empty log message *** rherveille 7841d 06h /i2c/trunk/
27 Cleaned up code rherveille 7841d 06h /i2c/trunk/
26 *** empty log message *** rherveille 7844d 13h /i2c/trunk/
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7872d 10h /i2c/trunk/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7872d 10h /i2c/trunk/
23 *** empty log message *** rherveille 7999d 15h /i2c/trunk/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8009d 20h /i2c/trunk/
21 no message rherveille 8095d 21h /i2c/trunk/
20 Added Appendix A rherveille 8095d 21h /i2c/trunk/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8099d 18h /i2c/trunk/
18 no message rherveille 8126d 13h /i2c/trunk/
17 C-include file.
Initial release		 rherveille 8214d 18h /i2c/trunk/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8226d 17h /i2c/trunk/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8231d 16h /i2c/trunk/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8231d 16h /i2c/trunk/
13 Fixed some synthesis warnings. rherveille 8242d 20h /i2c/trunk/
12 no message rherveille 8248d 12h /i2c/trunk/
11 Changed RST_LVL define to parameter. rherveille 8251d 19h /i2c/trunk/
10 Created new directory structure.
Added Verilog version.		 rherveille 8273d 16h /i2c/trunk/
9 Created directory structure (documentation, vhdl, verilog) rherveille 8343d 11h /i2c/trunk/
8 Created directory structure (documentation, vhdl, verilog) rherveille 8343d 11h /i2c/trunk/
7 added some remarks, fixed some sensitivity lists rherveille 8412d 13h /i2c/trunk/
6 fixed typo txt -> txr rherveille 8416d 17h /i2c/trunk/
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8423d 15h /i2c/trunk/
4 WISHBONE I2C Master Core: initial release rherveille 8475d 18h /i2c/trunk/
2 initial release rherveille 8537d 18h /i2c/trunk/
1 Standard project directories initialized by cvs2svn. 8537d 18h /i2c/trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.