OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] - Rev 31

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
31 Core is now a Multimaster I2C controller. rherveille 7805d 09h /i2c/trunk/
30 Small code simplifications rherveille 7805d 09h /i2c/trunk/
29 Core is now a Multimaster I2C controller rherveille 7805d 10h /i2c/trunk/
28 *** empty log message *** rherveille 7831d 03h /i2c/trunk/
27 Cleaned up code rherveille 7831d 03h /i2c/trunk/
26 *** empty log message *** rherveille 7834d 10h /i2c/trunk/
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7862d 07h /i2c/trunk/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7862d 07h /i2c/trunk/
23 *** empty log message *** rherveille 7989d 12h /i2c/trunk/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7999d 17h /i2c/trunk/
21 no message rherveille 8085d 18h /i2c/trunk/
20 Added Appendix A rherveille 8085d 18h /i2c/trunk/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8089d 14h /i2c/trunk/
18 no message rherveille 8116d 10h /i2c/trunk/
17 C-include file.
Initial release		 rherveille 8204d 15h /i2c/trunk/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8216d 14h /i2c/trunk/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8221d 13h /i2c/trunk/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8221d 13h /i2c/trunk/
13 Fixed some synthesis warnings. rherveille 8232d 17h /i2c/trunk/
12 no message rherveille 8238d 09h /i2c/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.