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[/] [i2c/] [trunk/] - Rev 33

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Rev Log message Author Age Path
33 Fixed a bug in the Command Register declaration. rherveille 7799d 06h /i2c/trunk/
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7809d 06h /i2c/trunk/
31 Core is now a Multimaster I2C controller. rherveille 7813d 07h /i2c/trunk/
30 Small code simplifications rherveille 7813d 07h /i2c/trunk/
29 Core is now a Multimaster I2C controller rherveille 7813d 08h /i2c/trunk/
28 *** empty log message *** rherveille 7839d 00h /i2c/trunk/
27 Cleaned up code rherveille 7839d 00h /i2c/trunk/
26 *** empty log message *** rherveille 7842d 08h /i2c/trunk/
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7870d 05h /i2c/trunk/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7870d 05h /i2c/trunk/
23 *** empty log message *** rherveille 7997d 10h /i2c/trunk/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8007d 15h /i2c/trunk/
21 no message rherveille 8093d 16h /i2c/trunk/
20 Added Appendix A rherveille 8093d 16h /i2c/trunk/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8097d 12h /i2c/trunk/
18 no message rherveille 8124d 08h /i2c/trunk/
17 C-include file.
Initial release		 rherveille 8212d 13h /i2c/trunk/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8224d 12h /i2c/trunk/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8229d 11h /i2c/trunk/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8229d 11h /i2c/trunk/
13 Fixed some synthesis warnings. rherveille 8240d 15h /i2c/trunk/
12 no message rherveille 8246d 06h /i2c/trunk/
11 Changed RST_LVL define to parameter. rherveille 8249d 14h /i2c/trunk/
10 Created new directory structure.
Added Verilog version.		 rherveille 8271d 10h /i2c/trunk/
9 Created directory structure (documentation, vhdl, verilog) rherveille 8341d 05h /i2c/trunk/
8 Created directory structure (documentation, vhdl, verilog) rherveille 8341d 06h /i2c/trunk/
7 added some remarks, fixed some sensitivity lists rherveille 8410d 08h /i2c/trunk/
6 fixed typo txt -> txr rherveille 8414d 12h /i2c/trunk/
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8421d 10h /i2c/trunk/
4 WISHBONE I2C Master Core: initial release rherveille 8473d 13h /i2c/trunk/

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