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[/] [i2c/] [trunk/] - Rev 34

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Rev Log message Author Age Path
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7756d 10h /i2c/trunk/
33 Fixed a bug in the Command Register declaration. rherveille 7778d 19h /i2c/trunk/
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7788d 19h /i2c/trunk/
31 Core is now a Multimaster I2C controller. rherveille 7792d 20h /i2c/trunk/
30 Small code simplifications rherveille 7792d 20h /i2c/trunk/
29 Core is now a Multimaster I2C controller rherveille 7792d 21h /i2c/trunk/
28 *** empty log message *** rherveille 7818d 14h /i2c/trunk/
27 Cleaned up code rherveille 7818d 14h /i2c/trunk/
26 *** empty log message *** rherveille 7821d 22h /i2c/trunk/
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7849d 18h /i2c/trunk/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7849d 18h /i2c/trunk/
23 *** empty log message *** rherveille 7976d 23h /i2c/trunk/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7987d 05h /i2c/trunk/
21 no message rherveille 8073d 05h /i2c/trunk/
20 Added Appendix A rherveille 8073d 05h /i2c/trunk/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8077d 02h /i2c/trunk/
18 no message rherveille 8103d 22h /i2c/trunk/
17 C-include file.
Initial release		 rherveille 8192d 02h /i2c/trunk/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8204d 01h /i2c/trunk/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8209d 00h /i2c/trunk/

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