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[/] [i2c/] [trunk/] - Rev 38

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Rev Log message Author Age Path
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7111d 17h /i2c/trunk/
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.
rherveille 7148d 09h /i2c/trunk/
36 Fixed cmd_ack generation item (no bug). rherveille 7263d 10h /i2c/trunk/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7297d 00h /i2c/trunk/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7300d 22h /i2c/trunk/
33 Fixed a bug in the Command Register declaration. rherveille 7323d 08h /i2c/trunk/
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.
rherveille 7333d 07h /i2c/trunk/
31 Core is now a Multimaster I2C controller. rherveille 7337d 08h /i2c/trunk/
30 Small code simplifications rherveille 7337d 08h /i2c/trunk/
29 Core is now a Multimaster I2C controller rherveille 7337d 09h /i2c/trunk/
28 *** empty log message *** rherveille 7363d 02h /i2c/trunk/
27 Cleaned up code rherveille 7363d 02h /i2c/trunk/
26 *** empty log message *** rherveille 7366d 10h /i2c/trunk/
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 7394d 06h /i2c/trunk/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7394d 06h /i2c/trunk/
23 *** empty log message *** rherveille 7521d 12h /i2c/trunk/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7531d 17h /i2c/trunk/
21 no message rherveille 7617d 17h /i2c/trunk/
20 Added Appendix A rherveille 7617d 17h /i2c/trunk/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 7621d 14h /i2c/trunk/

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