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[/] [i2c/] [trunk/] - Rev 38

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Rev Log message Author Age Path
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7566d 03h /i2c/trunk/
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7602d 19h /i2c/trunk/
36 Fixed cmd_ack generation item (no bug). rherveille 7717d 20h /i2c/trunk/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7751d 10h /i2c/trunk/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7755d 08h /i2c/trunk/
33 Fixed a bug in the Command Register declaration. rherveille 7777d 18h /i2c/trunk/
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7787d 17h /i2c/trunk/
31 Core is now a Multimaster I2C controller. rherveille 7791d 18h /i2c/trunk/
30 Small code simplifications rherveille 7791d 18h /i2c/trunk/
29 Core is now a Multimaster I2C controller rherveille 7791d 19h /i2c/trunk/
28 *** empty log message *** rherveille 7817d 12h /i2c/trunk/
27 Cleaned up code rherveille 7817d 12h /i2c/trunk/
26 *** empty log message *** rherveille 7820d 20h /i2c/trunk/
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7848d 16h /i2c/trunk/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7848d 16h /i2c/trunk/
23 *** empty log message *** rherveille 7975d 22h /i2c/trunk/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7986d 03h /i2c/trunk/
21 no message rherveille 8072d 03h /i2c/trunk/
20 Added Appendix A rherveille 8072d 03h /i2c/trunk/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8076d 00h /i2c/trunk/

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