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Rev Log message Author Age Path
39 Forgot an 'end if' :-/ rherveille 7507d 03h /i2c/trunk/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7510d 11h /i2c/trunk/
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.
rherveille 7547d 03h /i2c/trunk/
36 Fixed cmd_ack generation item (no bug). rherveille 7662d 04h /i2c/trunk/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7695d 18h /i2c/trunk/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7699d 16h /i2c/trunk/
33 Fixed a bug in the Command Register declaration. rherveille 7722d 01h /i2c/trunk/
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.
rherveille 7732d 01h /i2c/trunk/
31 Core is now a Multimaster I2C controller. rherveille 7736d 02h /i2c/trunk/
30 Small code simplifications rherveille 7736d 02h /i2c/trunk/
29 Core is now a Multimaster I2C controller rherveille 7736d 03h /i2c/trunk/
28 *** empty log message *** rherveille 7761d 20h /i2c/trunk/
27 Cleaned up code rherveille 7761d 20h /i2c/trunk/
26 *** empty log message *** rherveille 7765d 04h /i2c/trunk/
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 7793d 00h /i2c/trunk/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7793d 00h /i2c/trunk/
23 *** empty log message *** rherveille 7920d 05h /i2c/trunk/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7930d 10h /i2c/trunk/
21 no message rherveille 8016d 11h /i2c/trunk/
20 Added Appendix A rherveille 8016d 11h /i2c/trunk/

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