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Rev Log message Author Age Path
59 fixed short scl high pulse after clock stretch rherveille 6439d 17h /i2c/trunk/
58 fixed (n)ack generation rherveille 6471d 18h /i2c/trunk/
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 6471d 18h /i2c/trunk/
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 7024d 16h /i2c/trunk/
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 7025d 18h /i2c/trunk/
54 Fixed scl, sda delay. rherveille 7025d 18h /i2c/trunk/
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7321d 16h /i2c/trunk/
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7321d 17h /i2c/trunk/
51 Fixed simulation issue when writing to CR register rherveille 7375d 17h /i2c/trunk/
50 *** empty log message *** rherveille 7390d 12h /i2c/trunk/
49 Added testbench rherveille 7390d 12h /i2c/trunk/
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7391d 20h /i2c/trunk/
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7400d 16h /i2c/trunk/
46 Fixed slave address MSB='1' bug rherveille 7475d 17h /i2c/trunk/
45 Added slave address configurability rherveille 7475d 17h /i2c/trunk/
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7560d 19h /i2c/trunk/
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7570d 17h /i2c/trunk/
39 Forgot an 'end if' :-/ rherveille 7590d 13h /i2c/trunk/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7593d 21h /i2c/trunk/
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.
rherveille 7630d 12h /i2c/trunk/

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