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[/] [i2c/] [trunk/] - Rev 59

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Rev Log message Author Age Path
59 fixed short scl high pulse after clock stretch rherveille 6431d 07h /i2c/trunk/
58 fixed (n)ack generation rherveille 6463d 09h /i2c/trunk/
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal		 rherveille 6463d 09h /i2c/trunk/
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.		 rherveille 7016d 07h /i2c/trunk/
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.		 rherveille 7017d 09h /i2c/trunk/
54 Fixed scl, sda delay. rherveille 7017d 09h /i2c/trunk/
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7313d 06h /i2c/trunk/
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7313d 07h /i2c/trunk/
51 Fixed simulation issue when writing to CR register rherveille 7367d 08h /i2c/trunk/
50 *** empty log message *** rherveille 7382d 03h /i2c/trunk/
49 Added testbench rherveille 7382d 03h /i2c/trunk/
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7383d 10h /i2c/trunk/
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7392d 07h /i2c/trunk/
46 Fixed slave address MSB='1' bug rherveille 7467d 07h /i2c/trunk/
45 Added slave address configurability rherveille 7467d 07h /i2c/trunk/
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7552d 10h /i2c/trunk/
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7562d 08h /i2c/trunk/
39 Forgot an 'end if' :-/ rherveille 7582d 03h /i2c/trunk/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7585d 11h /i2c/trunk/
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7622d 03h /i2c/trunk/
36 Fixed cmd_ack generation item (no bug). rherveille 7737d 04h /i2c/trunk/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7770d 18h /i2c/trunk/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7774d 16h /i2c/trunk/
33 Fixed a bug in the Command Register declaration. rherveille 7797d 01h /i2c/trunk/
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7807d 01h /i2c/trunk/
31 Core is now a Multimaster I2C controller. rherveille 7811d 02h /i2c/trunk/
30 Small code simplifications rherveille 7811d 02h /i2c/trunk/
29 Core is now a Multimaster I2C controller rherveille 7811d 03h /i2c/trunk/
28 *** empty log message *** rherveille 7836d 20h /i2c/trunk/
27 Cleaned up code rherveille 7836d 20h /i2c/trunk/

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