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[/] [i2c/] [trunk/] - Rev 64

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Rev Log message Author Age Path
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation		 rherveille 5596d 12h /i2c/trunk
63 Added clock synchronization logic
Fixed slave_wait signal		 rherveille 5596d 12h /i2c/trunk
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits		 rherveille 5597d 02h /i2c/trunk
61 Removed synopsys link; it's not used rherveille 6251d 14h /i2c/trunk
60 Added missing semicolons ';' on endif rherveille 6428d 10h /i2c/trunk
59 fixed short scl high pulse after clock stretch rherveille 6433d 12h /i2c/trunk
58 fixed (n)ack generation rherveille 6465d 14h /i2c/trunk
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal		 rherveille 6465d 14h /i2c/trunk
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.		 rherveille 7018d 11h /i2c/trunk
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.		 rherveille 7019d 13h /i2c/trunk
54 Fixed scl, sda delay. rherveille 7019d 13h /i2c/trunk
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7315d 11h /i2c/trunk
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7315d 12h /i2c/trunk
51 Fixed simulation issue when writing to CR register rherveille 7369d 12h /i2c/trunk
50 *** empty log message *** rherveille 7384d 07h /i2c/trunk
49 Added testbench rherveille 7384d 07h /i2c/trunk
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7385d 15h /i2c/trunk
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7394d 11h /i2c/trunk
46 Fixed slave address MSB='1' bug rherveille 7469d 12h /i2c/trunk
45 Added slave address configurability rherveille 7469d 12h /i2c/trunk

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