OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] - Rev 68

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
68 New directory structure. root 5010d 16h /i2c/trunk/
67 Fixed slave_wait clocked event syntax rherveille 5043d 18h /trunk/
66 Fixed type iscl_oen instead of scl_oen rherveille 5058d 17h /trunk/
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5059d 03h /trunk/
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 5059d 04h /trunk/
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 5059d 04h /trunk/
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 5059d 18h /trunk/
61 Removed synopsys link; it's not used rherveille 5714d 05h /trunk/
60 Added missing semicolons ';' on endif rherveille 5891d 02h /trunk/
59 fixed short scl high pulse after clock stretch rherveille 5896d 03h /trunk/
58 fixed (n)ack generation rherveille 5928d 05h /trunk/
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 5928d 05h /trunk/
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 6481d 03h /trunk/
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 6482d 05h /trunk/
54 Fixed scl, sda delay. rherveille 6482d 05h /trunk/
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 6778d 02h /trunk/
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 6778d 03h /trunk/
51 Fixed simulation issue when writing to CR register rherveille 6832d 04h /trunk/
50 *** empty log message *** rherveille 6846d 22h /trunk/
49 Added testbench rherveille 6846d 23h /trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.