OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] - Rev 72

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
72 Fixed AL generation
Added median filter on SDA and SCL inputs		 rherveille 5217d 16h /i2c/trunk/
71 Fixed double wishbone write in a single access rherveille 5217d 16h /i2c/trunk/
68 New directory structure. root 5526d 10h /i2c/trunk/
67 Fixed slave_wait clocked event syntax rherveille 5559d 12h /trunk/
66 Fixed type iscl_oen instead of scl_oen rherveille 5574d 12h /trunk/
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5574d 22h /trunk/
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation		 rherveille 5574d 22h /trunk/
63 Added clock synchronization logic
Fixed slave_wait signal		 rherveille 5574d 22h /trunk/
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits		 rherveille 5575d 12h /trunk/
61 Removed synopsys link; it's not used rherveille 6230d 00h /trunk/
60 Added missing semicolons ';' on endif rherveille 6406d 21h /trunk/
59 fixed short scl high pulse after clock stretch rherveille 6411d 22h /trunk/
58 fixed (n)ack generation rherveille 6444d 00h /trunk/
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal		 rherveille 6444d 00h /trunk/
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.		 rherveille 6996d 21h /trunk/
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.		 rherveille 6997d 23h /trunk/
54 Fixed scl, sda delay. rherveille 6997d 23h /trunk/
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7293d 21h /trunk/
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7293d 22h /trunk/
51 Fixed simulation issue when writing to CR register rherveille 7347d 22h /trunk/
50 *** empty log message *** rherveille 7362d 17h /trunk/
49 Added testbench rherveille 7362d 17h /trunk/
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7364d 01h /trunk/
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7372d 21h /trunk/
46 Fixed slave address MSB='1' bug rherveille 7447d 22h /trunk/
45 Added slave address configurability rherveille 7447d 22h /trunk/
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7533d 00h /trunk/
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7542d 22h /trunk/
39 Forgot an 'end if' :-/ rherveille 7562d 18h /trunk/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7566d 02h /trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.