OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] - Rev 74

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
74 Added SCL/SDA line filter rherveille 5275d 18h /i2c/trunk/
73 Fixed double wishbone write in a single access rherveille 5275d 18h /i2c/trunk/
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 5275d 18h /i2c/trunk/
71 Fixed double wishbone write in a single access rherveille 5275d 18h /i2c/trunk/
68 New directory structure. root 5584d 12h /i2c/trunk/
67 Fixed slave_wait clocked event syntax rherveille 5617d 15h /trunk/
66 Fixed type iscl_oen instead of scl_oen rherveille 5632d 14h /trunk/
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5633d 00h /trunk/
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 5633d 00h /trunk/
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 5633d 00h /trunk/
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 5633d 14h /trunk/
61 Removed synopsys link; it's not used rherveille 6288d 02h /trunk/
60 Added missing semicolons ';' on endif rherveille 6464d 23h /trunk/
59 fixed short scl high pulse after clock stretch rherveille 6470d 00h /trunk/
58 fixed (n)ack generation rherveille 6502d 02h /trunk/
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 6502d 02h /trunk/
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 7054d 23h /trunk/
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 7056d 01h /trunk/
54 Fixed scl, sda delay. rherveille 7056d 01h /trunk/
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7351d 23h /trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.