URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] - Rev 76

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Rev	Log message	Author	Age	Path
76	Updated filter_cnt generation	rherveille	5066d 15h	/i2c/trunk/
75	Fixed sSDA generation	rherveille	5072d 12h	/i2c/trunk/
74	Added SCL/SDA line filter	rherveille	5211d 08h	/i2c/trunk/
73	Fixed double wishbone write in a single access	rherveille	5211d 08h	/i2c/trunk/
72	Fixed AL generation Added median filter on SDA and SCL inputs	rherveille	5211d 08h	/i2c/trunk/
71	Fixed double wishbone write in a single access	rherveille	5211d 08h	/i2c/trunk/
68	New directory structure.	root	5520d 02h	/i2c/trunk/
67	Fixed slave_wait clocked event syntax	rherveille	5553d 04h	/trunk/
66	Fixed type iscl_oen instead of scl_oen	rherveille	5568d 04h	/trunk/
65	Changed wb_adr_i from unsigned to std_logic_vector	rherveille	5568d 14h	/trunk/
64	Added SCL clock synchronization logic Fixed slave_wait signal generation	rherveille	5568d 14h	/trunk/
63	Added clock synchronization logic Fixed slave_wait signal	rherveille	5568d 14h	/trunk/
62	Fixed synopsys miss spell (synopsis) Fixed cr[0] register width Fixed ! usage instead of ~ Fixed bit controller parameter width to 18bits	rherveille	5569d 04h	/trunk/
61	Removed synopsys link; it's not used	rherveille	6223d 16h	/trunk/
60	Added missing semicolons ';' on endif	rherveille	6400d 12h	/trunk/
59	fixed short scl high pulse after clock stretch	rherveille	6405d 14h	/trunk/
58	fixed (n)ack generation	rherveille	6437d 15h	/trunk/
57	fixed short scl high pulse after clock stretch fixed slave model not returning correct '(n)ack' signal	rherveille	6437d 16h	/trunk/
56	Fixed Tsu:sta timing check. Added Thd:sta timing check.	rherveille	6990d 13h	/trunk/
55	Fixed register overwrite issue. Removed full_case pragma, replaced it by a default statement.	rherveille	6991d 15h	/trunk/

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Subversion Repositories i2c

[/] [i2c/] [trunk/] - Rev 76

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