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[/] [i2c/] [trunk/] - Rev 76

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Rev Log message Author Age Path
76 Updated filter_cnt generation rherveille 5073d 20h /i2c/trunk
75 Fixed sSDA generation rherveille 5079d 17h /i2c/trunk
74 Added SCL/SDA line filter rherveille 5218d 13h /i2c/trunk
73 Fixed double wishbone write in a single access rherveille 5218d 13h /i2c/trunk
72 Fixed AL generation
Added median filter on SDA and SCL inputs		 rherveille 5218d 13h /i2c/trunk
71 Fixed double wishbone write in a single access rherveille 5218d 13h /i2c/trunk
68 New directory structure. root 5527d 07h /i2c/trunk
67 Fixed slave_wait clocked event syntax rherveille 5560d 10h /trunk
66 Fixed type iscl_oen instead of scl_oen rherveille 5575d 09h /trunk
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5575d 19h /trunk
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation		 rherveille 5575d 19h /trunk
63 Added clock synchronization logic
Fixed slave_wait signal		 rherveille 5575d 19h /trunk
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits		 rherveille 5576d 09h /trunk
61 Removed synopsys link; it's not used rherveille 6230d 21h /trunk
60 Added missing semicolons ';' on endif rherveille 6407d 18h /trunk
59 fixed short scl high pulse after clock stretch rherveille 6412d 19h /trunk
58 fixed (n)ack generation rherveille 6444d 21h /trunk
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal		 rherveille 6444d 21h /trunk
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.		 rherveille 6997d 18h /trunk
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.		 rherveille 6998d 20h /trunk
54 Fixed scl, sda delay. rherveille 6998d 20h /trunk
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7294d 18h /trunk
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7294d 19h /trunk
51 Fixed simulation issue when writing to CR register rherveille 7348d 20h /trunk
50 *** empty log message *** rherveille 7363d 14h /trunk
49 Added testbench rherveille 7363d 14h /trunk
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7364d 22h /trunk
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7373d 18h /trunk
46 Fixed slave address MSB='1' bug rherveille 7448d 19h /trunk
45 Added slave address configurability rherveille 7448d 19h /trunk

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