Subversion Repositories i2c

[/] [i2c/] [trunk/] [bench/] - Rev 68


Filtering Options

Clear current filter

Rev Log message Author Age Path
68 New directory structure. root 5012d 16h /i2c/trunk/bench/
58 fixed (n)ack generation rherveille 5930d 05h /trunk/bench/
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 6483d 03h /trunk/bench/
54 Fixed scl, sda delay. rherveille 6484d 05h /trunk/bench/
50 *** empty log message *** rherveille 6848d 23h /trunk/bench/
49 Added testbench rherveille 6848d 23h /trunk/bench/
46 Fixed slave address MSB='1' bug rherveille 6934d 04h /trunk/bench/
45 Added slave address configurability rherveille 6934d 04h /trunk/bench/
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7019d 06h /trunk/bench/
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 7334d 20h /trunk/bench/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 7562d 04h /trunk/bench/
10 Created new directory structure.
Added Verilog version.
rherveille 7736d 02h /trunk/bench/

powered by: WebSVN 2.1.0

© copyright 1999-2022, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.