OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [bench/] - Rev 68

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
68 New directory structure. root 3970d 14h /i2c/trunk/bench/
58 fixed (n)ack generation rherveille 4888d 04h /trunk/bench/
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 5441d 01h /trunk/bench/
54 Fixed scl, sda delay. rherveille 5442d 04h /trunk/bench/
50 *** empty log message *** rherveille 5806d 21h /trunk/bench/
49 Added testbench rherveille 5806d 21h /trunk/bench/
46 Fixed slave address MSB='1' bug rherveille 5892d 02h /trunk/bench/
45 Added slave address configurability rherveille 5892d 02h /trunk/bench/
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 5977d 05h /trunk/bench/
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 6292d 19h /trunk/bench/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 6520d 02h /trunk/bench/
10 Created new directory structure.
Added Verilog version.
rherveille 6694d 01h /trunk/bench/

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.