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[/] [i2c/] [trunk/] [bench/] - Rev 76


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Rev Log message Author Age Path
68 New directory structure. root 5558d 21h /i2c/trunk/bench/
58 fixed (n)ack generation rherveille 6476d 11h /trunk/bench/
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 7029d 08h /trunk/bench/
54 Fixed scl, sda delay. rherveille 7030d 11h /trunk/bench/
50 *** empty log message *** rherveille 7395d 04h /trunk/bench/
49 Added testbench rherveille 7395d 04h /trunk/bench/
46 Fixed slave address MSB='1' bug rherveille 7480d 09h /trunk/bench/
45 Added slave address configurability rherveille 7480d 09h /trunk/bench/
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7565d 12h /trunk/bench/
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 7881d 02h /trunk/bench/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 8108d 10h /trunk/bench/
10 Created new directory structure.
Added Verilog version.
rherveille 8282d 08h /trunk/bench/

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